It is known to provide data processing systems, such as the ARM processors designed by ARM Limited, Cambridge, England, which are responsive to received interrupt signals to interrupt a normal sequence of program instructions and redirect processing to an interrupt handler sequence of processing instructions. This type of behaviour is important in providing the ability for a data processing system to rapidly respond to external events. As an example, a data processing system may be used to control an anti-lock braking system with the occurrence of a skid condition being signalled to the processor via an interrupt signal which is able to quickly interrupt whatever processing is currently underway and commence execution of appropriate instructions to deal with the critical skid condition.
In order that a data processing system can avoid incorrect operation due to repeated or continuous assertion of an interrupt signal which would otherwise cause the interrupt handling code itself to be interrupted, it is known to provide systems with an interrupt masking bit which is set by hardware upon first occurrence of an interrupt and serves to block the effect of subsequent interrupt signals received on that interrupt signal line until the masking bit has been cleared, typically under software control once a certain portion of the interrupt handling code has been executed. With ARM processors, an example of this type of behaviour is provided by the F bit within the program status register. The ability to alter the F bit under program control is useful in that it provides considerable flexibility in the way that interrupts and interrupt masking may be used, e.g. it is possible to use the F bit under software control to enforce the atomic execution of a sequence program instructions by precluding the possibility of an interrupt being acted upon during that sequence of instructions (the F bit may be set to mask interrupts at the start of the sequence of instructions and reset at the end of the sequence of instructions thereby ensuring atomic execution).
A problem with this arrangement is that the ability for the interrupt masking bit to be set under software control creates the possibility that a programming bug or other software based malfunction may lead to the interrupt masking bit being inappropriately set and so preventing the ability of the system to promptly react to what may be a time critical interrupt signal.